1. Field of the Invention
The present invention relates to a memory system having a plurality of types of memory chips and a memory controller for controlling these memory chips.
2. Description of the Related Art
With the progression of semiconductor manufacturing technology and semiconductor design technology, it has become possible to implement one whole system on a single semiconductor chip. A semiconductor that operates as a single system is generally referred to as a system LSI. A system LSI contains, for example, an MPU core for controlling the entire system, peripheral cores (IP cores) having a predetermined function, and a memory core. The memory core stores programs necessary for the operation of the system, data for the system to handle, and so on.
Recently, there have been developed portable apparatuses that handle large amounts of data such as moving images. When these portable apparatuses use memory capacities beyond those of the memory cores mounted on their system LSIs, it is usual to constitute the systems with semiconductor memories (memory chips) externally attached to the system LSIs. The reason for this is that if high capacity memory cores are incorporated into the system LSIs, the system LSIs increase in chip size and might drop in yield.
Furthermore, logic products such as an MPU and memory products such as a DRAM are optimized in design for respective features, and manufactured under respective optimum conditions. Accordingly, designing and manufacturing the memory chips aside from the system LSIs (logic chips) can improve system performance.
FIG. 1 shows an example of the system (memory system) in which a plurality of types of memory chips are externally attached to a system LSI. Here, a memory system refers to a set of functions of a system constituting the above-mentioned portable apparatus or the like that are necessary for memory operation.
The memory system comprises a system LSI 2 and a plurality of types of memory chips 3a, 3b, and 3c to be mounted on a printed-circuit board 1. The system LSI 2 has an MPU 4 for controlling the entire system, peripheral cores (IP) 5a and 5b having a predetermined function, and memory controllers 6a, 6b, and 6c corresponding to the memory chips 3a, 3b, and 3c, respectively. The memory chips 3a, 3b, and 3c are respectively connected to the memory controllers 6a, 6b, and 6c through buses 7a, 7b, and 7c which are laid on the printed-circuit board 1.
Conventionally, in the case of constructing the memory system from the system LSI 2 and the plurality of types of memory chips 3a, 3b, and 3c, it has been required, as described above, that the memory chips 3a, 3b, and 3c be individually provided with the memory controllers 6a, 6b, and 6c. For example, SDRAMs and flash memories have different command systems and operation timing for performing write operations and read operations. Therefore, SDRAMs and flash memories have necessitated their respective memory controllers when externally attached to a system LSI. As a result, there has been a problem that the system LSI 2 grows in chip size and increases in chip cost.
Since the terminals of the memory chips 3a, 3b, and 3c are connected to the terminals of the system LSI 2 through the buses 7a, 7b, and 7c, respectively, the number of terminals of the system LSI 2 becomes enormous. Consequently, the system LSI 2 might be greater in chip size depending on the number of terminals. In worst cases, it has been necessary to develop a new package for the number of terminals of the system LSI 2.
Since the plurality of memory controllers 6a, 6b, and 6c are mounted on the system LSI 2, the system LSI 2 has been greater in circuit scale, requiring an enormous amount of time for design verification.
The formation of the buses 7a, 7b, and 7c necessitates large numbers of wires on the printed-circuit board 1. Consequently, there has been a problem that the wiring layers of the printed-circuit board 1 grows in number, increasing the design cost and manufacturing cost of the printed-circuit board 1.
Clock synchronous SDRAMs have been developed to improve the data transmission rates of DRAMs. For other clock asynchronous semiconductor memories (including nonvolatile memories), products of clock synchronous type are also likely to be developed.
It is an object of the present invention to reduce the costs of a memory system that has a plurality of types of memory chips and a memory controller for controlling these memory chips.
Another object of the present invention is to provide a common interface in a memory system comprising a system LSI with a plurality of types of memory chips externally attached, the common interface connecting the memory chips and the system LSI for controlling the memory chips.
Still another object of the present invention is to attach clock synchronous nonvolatile memories externally to a system LSI with facility and lower costs.
According to one of the aspects of the memory system of the present invention, the memory system comprises: a plurality of types of memory chips operating in synchronization with a clock signal; a controller for issuing access requests to the memory chips; a memory controller for controlling the memory chips; and a common bus for connecting the memory chips and the memory controller to transmit memory input signals and memory output signals. The memory chips include, for example, a volatile memory such as a synchronous DRAM and a nonvolatile memory such as a clock synchronous NAND type flash memory.
The memory controller converts, according to operation specifications of the memory chips to operate, controller output signals which the controller outputs to the memory controller when operating memory chips, into the memory input signals receivable to the memory chips. The memory chips receive the memory input signals and perform a read operation, a write operation, or the like. Among the controller output signals and the memory input signals are address signals, command signals, and write data signals.
The memory chips output read data signals obtained through their read operations to the common bus as the memory output signals. The memory controller receives the memory output signals through the common bus, and converts the received signals into read data signals (controller input signals) receivable to the controller. Then, the controller receives the controller input signals, thereby completing the read operations of the memory system.
As described above, the memory controller converts controller output signals into memory input signals receivable to the individual memory chips. This allows the single memory controller to access the plurality of types of memory chips. As a result, the plurality of memory chips can be connected to the memory controller through the common bus, which can minimize a number of signal lines. In addition, the memory controller can be reduced in circuit scale. The memory controller need not be designed anew upon each development of memory chips as heretofore.
According to another aspect of the memory system of the present invention, the memory output signals and the memory input signals received respectively by the memory controller and the memory chips through the common bus have the same input timing specification irrespective of which of the memory chips is to operate. Similarly, the memory input signals and the memory output signals output respectively from the memory controller and the memory chips through the common bus have the same output timing specification irrespective of which of the memory chips is to operate. On this account, the memory controller can reliably access the plurality of types of memory chips having different operation specifications by simply adjusting the output order of the memory input signals and the acceptance order of the memory output signals according to the command specifications and the like of the memory chips.
For example, the input timing specification is defined by a setup time tIS and a hold time tIH with respect to an edge of the clock signal. Similarly, the output timing specification is defined by a setup time tOS and a hold time tOH with respect to an edge of the clock signal. When the setup time tOS and the hold time tOH are set longer than the setup time tIS and the hold time tIH, the memory controller and the individual memory chips can surely receive the memory output signals and the memory input signals, respectively.
According to another aspect of the memory system of the present invention, the memory controller includes an operation memory unit, an input/output controlling unit, and a conversion control unit. The operation memory unit stores the operation specifications of the respective memory chips. The conversion control unit operates the input/output controlling unit in accordance with information from the operation memory unit. For example, the conversion control unit has only to control the operation timing and the input/output direction of the input/output controlling unit in accordance with the information from the operation memory unit. The input/output controlling unit operates under instructions from the conversion control unit, to input the controller output signals from the controller and output the controller input signals to the controller, and to output the memory input signals to the memory chips and input the memory output signals from the memory chips. Operating the input/output controlling unit, or the interface with the memory chips, according to the operation specifications of the respective memory chips makes it possible to operate the memory chips reliably without using complicated control circuits.
According to another aspect of the memory system of the present invention, the memory controller includes a signal holding unit. The signal holding unit temporarily holds the controller output signals and the memory output signals received by the input/output controlling unit. For example, when the memory chip to be accessed is asynchronous DRAM of address multiplex system, an address signal (controller output signal) held in the signal holding unit is divided under the instruction from the conversion control unit and output in succession as a row address signal and a column address signal. Similarly, when the memory chip to be accessed is a clock synchronous NAND type flash memory, a start address (controller output signal) held in the signal holding unit is divided into a plurality of packets under the instruction from the conversion control unit for successive outputs. That is, signals can be output to the memory chips according to the operation specifications of the respective memory chips.
According to another aspect of the memory system of the present invention, if one of the memory chips is in operation when the memory controller receives the controller output signal for operating another of the memory chips, the signal holding unit temporarily holds this controller output signal. That is, the controller output signal output from the controller can be held until the common bus becomes available. Since the controller output signal is held by the signal holding unit of the memory controller, the controller can access other devices such as a peripheral circuit, or peripheral cores, independent of the operation wait for the another memory chip. Since the controller is prevented from executing useless cycles, the entire system improves in operating efficiency.
According to another aspect of the memory system of the present invention, the memory controller includes an arbiter. The arbiter adjusts the order of accesses to the memory chips depending on the operation states of the memory chips and the holding order of the controller output signals corresponding to a plurality of memory chips that are held in the signal holding unit The arbiter is composed of, for example, programmable logics capable of reconstructing their respective circuit functions.
If a memory chip is using the common bus when the controller issues an access request to another memory chip, the arbiter keeps the access to the another memory chip waiting until the common bus becomes available. The output controller signal output from the controller to access the another memory chip is temporarily held in the signal holding unit.
In some cases where the controller issues access requests to a plurality of memory chips for read operations, one of the memory chips can complete its read operation within the period from the start of the operation of another memory chip to the output of a read data signal. In such cases, the arbiter operates the one memory chip by utilizing the vacancy of the common bus during the operation period of the another.
By dint of the arbiter, the single memory controller can operate the plurality of types of memory chips with efficiency. As a result, the memory system can be improved in data transmission rate.
According to another aspect of the memory system of the present invention, the memory controller and the controller are mounted on an identical chip, being formed into a system LSI, for example. The memory controller itself can handle the plurality of types of memory chips, by which reduces the circuit scale. As a result, the system LSI where the memory controller is mounted can be reduced in chip size, lowering the cost of the memory system. Since the system LSI becomes smaller in circuit scale, it is possible to reduce the time necessary for the design verification of the system LSI.
According to another aspect of the memory system of the present invention, the common bus is formed on a printed-circuit board for mounting the controller and the memory chips. Sharing the memory controller among the plurality of memory chips can reduce the number of signal lines to be laid on the printed-circuit board, lowering the design cost and manufacturing cost of the printed-circuit board.
According to another aspect of the memory system of the present invention, the controller and the memory controller are stacked in three dimensions. The common bus is formed as interconnection wiring for connecting the controller and the memory chips. Sharing the memory controller among the plurality of memory chips can reduce the number of interconnection wires, thereby allowing an improvement in the reliability of the memory system stacked in three dimension.